DocumentCode
2888022
Title
A GaAs 1K SRAM with 2ns cycle time
Author
Gabillard, B. ; Rocher, C. ; Ducourant, T. ; Prost, M.
Author_Institution
Electronics and Physics Applications Laboratories, Limeil-Brevannes, France
Volume
XXX
fYear
1987
fDate
0-0 Feb. 1987
Firstpage
136
Lastpage
137
Abstract
An ECL compatible SRAM that attains rise and fall times of 200ps with a power consumtpion of 210mW will be described. Word line clamping and data bus delay reduction allow control of the access time in spite of threshold voltage varation of 90mV.
Keywords
Cache memory; Circuit simulation; Delay effects; Differential amplifiers; Driver circuits; Gallium arsenide; Paper technology; Random access memory; Switches; Threshold voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference. Digest of Technical Papers. 1987 IEEE International
Conference_Location
New York, NY, USA
Type
conf
DOI
10.1109/ISSCC.1987.1157128
Filename
1157128
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