Board trace fatigue models and design guidelines for electronics under shock-impact

Driven by the trends towards miniaturization and increased functionality, modern electronic systems are being built into more intricate and smaller packages. The mechanical robustness of these smaller and more complex packages is of great concern to the electronics industry. With advances in packaging technology, more reliable interconnects are being designed as a result of which the accountability for failure shifts to copper traces which form the primary failure mode. Previous researchers have addressed copper trace fatigue reliability [Farley 2009] and existence of copper-trace failures in drop-shock [Tee 2009]. This paper addresses the need for life prediction models for PWB copper traces in shock and vibration environments. The study focuses on high cycle fatigue of copper traces which is simulated by subjecting the PWB to vibrations in first mode until failure. Owing to the complexity of the test vehicle, global-local finite element models were developed for simulating the board response. The study addresses the need for empirical rules for trace layout on the PWB which ensure maximum reliability. The effect of trace orientation, trace-pad fillet angle and trace width on its reliability has been investigated. Using Digital Image Correlation based strain responses and Finite Element Model based stress responses, mathematical models for damage accumulation and life prediction of copper traces have been formulated and validated with experimental failure statistics.