Circuit schematic generation and optimization in VLSI circuits

We present a novel methodology converting Boolean expressions into circuit schematic directly such that the number of transistors is minimized. Three algorithms are developed to help this conversion. Here the pull-up/pull-down complementary circuit and transmission gate are investigated in the design procedure. The novel circuit schematic combining the above structures is developed to minimize the number of transistors. Note that the number of transistors effects on the layout area, power dissipation and overall performance in circuit design.