DocumentCode
2888407
Title
A 32b CMOS microprocessor with on-chip instruction and data caching and memory management
Author
Archer, D. ; Deverell, D. ; Fox, F. ; Gronowski, P. ; Jain, Abhishek ; Leary, M. ; Olesin, A. ; Persels, S. ; Rubinfeld, P. ; Schumacher, D. ; Supnik, B. ; Thrush, T.
Author_Institution
Digital Equipment Corp., Hudson, MA, USA
Volume
XXX
fYear
1987
fDate
0-0 Feb. 1987
Firstpage
32
Lastpage
33
Abstract
A processor implemented with 180K transistors in 2μm CMOS technology will be presented. The chip size is 9.7mm × 9.4mm, and the instruction set is compatible with a minicomputer.
Keywords
Clocks; Decoding; Logic; Memory management; Microprocessors; Prefetching; Protection; Pulse generation; Registers; Signal generators;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference. Digest of Technical Papers. 1987 IEEE International
Conference_Location
New York, NY, USA
Type
conf
DOI
10.1109/ISSCC.1987.1157147
Filename
1157147
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