Design and analysis of metastable-hardened flip-flops in sub-threshold region

Flip-flop metastability is becoming an important consideration for designing reliable synchronous and asynchronous systems, especially in the sub-threshold region where it degrades exponentially with the reduction in supply voltage. In this paper, detailed analysis is given on the design of metastable-hardened flip-flops in the sub-threshold region. Proper transistor sizing using either transconductance or load variation along with implementing the inverter pair in the flip-flop master-stage with low-V_th can result in significant reduction in the time-resolving constant τ. Extensive simulation results have shown that the optimum metastability-power-delay-product (MPDP) design allows the flip-flops to improve its metastability with a more balanced design tradeoff between performance and power consumption.