DocumentCode
2888632
Title
An algorithm for minimising the number of test cycles
Author
Diwan, A.A.
Author_Institution
Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Bombay, India
fYear
1991
fDate
4-8 Jan 1991
Firstpage
154
Lastpage
156
Abstract
The scan-path method for testing a VLSI circuit uses a shift register to store the test vectors, and a sequence of test patterns is applied by shifting in new patterns one bit at a time. This paper presents an algorithm to find the order in which the test patterns should be applied in order to minimise the number of shift operations required. The algorithm can be shown to be optimal under certain conditions
Keywords
VLSI; fault location; integrated circuit testing; production testing; shift registers; optimal algorithm; scan-path method; shift operations; shift register; test cycles; test patterns; Circuit faults; Circuit testing; Computer science; Production; Shift registers; Very large scale integration; Virtual manufacturing;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, 1991. Proceedings., Fourth CSI/IEEE International Symposium on
Conference_Location
New Delhi
Print_ISBN
0-8186-2125-7
Type
conf
DOI
10.1109/ISVD.1991.185109
Filename
185109
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