How the problem size influences the performance of an SIMD TDNN implementation

In this paper we describe the mapping and implementation of time delay neural networks (TDNN) to a grid based SIMD computer (MasPar MP-1216). After a short introduction to TDNNs we discuss several aspects of parallel implementations and motivate our decision to use a combination of unit parallelism and training pattern parallelism for the final implementation. The theoretical aspects and the complexity of computation and communication is described in detail. During several sets of tests these theoretical derivations are proved. It is shown that the performance of the implementation depends strongly on the number of feature neurons of the network and on the length of the input pattern. On the other hand it is shown that the performance is nearly independent of the delay length of the receptive fields. The multitude of experiments shows that our implementation does not only perform well for a set of optimal networks but also for real world problem networks with reasonable sized parameters