DocumentCode
2888651
Title
Overlap elimination in floorplans
Author
Vijayan, G.
Author_Institution
IBM Res. Div., Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
fYear
1991
fDate
4-8 Jan 1991
Firstpage
157
Lastpage
162
Abstract
Describes an algorithm for eliminating/reducing overlaps among blocks (macros) in VLSI chip floorplans. These blocks are assumed to be rectangular and can be either preplaced or movable. A movable block can have a fixed or a flexible shape. The authors describe applications for such an algorithm in the floorplanning process. The approach discussed in the paper is targeted towards macro cell based sea-of-gates designs
Keywords
VLSI; circuit layout CAD; logic CAD; logic arrays; VLSI chip; blocks; floorplanning process; floorplans; macro cell; movable block; overlaps; preplaced lock; sea-of-gates designs; Algorithm design and analysis; Compaction; Cost function; Iterative methods; Linear programming; Shape; Simulated annealing; Timing; Very large scale integration; Wire;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, 1991. Proceedings., Fourth CSI/IEEE International Symposium on
Conference_Location
New Delhi
Print_ISBN
0-8186-2125-7
Type
conf
DOI
10.1109/ISVD.1991.185110
Filename
185110
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