A 1kb 9T subthreshold SRAM with bit-interleaving scheme in 65nm CMOS

Subthreshold SRAM is a significant approach to reduce power consumption in energy-constrained SoC design. For the ultra-low power consideration, the primary concerns of SRAM are stability and reliability instead of performance. In this paper, the proposed 9T bit-cell enhances write ability by cutting off the positive feedback loop of inverter pair. In the read mode, the isolated read path and storage node enlarge the read SNM. Besides, a 9T subthreshold SRAM is proposed to enable implementation of bit-interleaving structure which achieves soft-error tolerance. The proposed SRAM is able to operate at a voltage as low as 0.3V. One extra virtual ground (VVSS) line is used to reduce the bit-line leakage to ensure the data can be read successfully. A 1kb bit-interleaved 9T SRAM is implemented in UMC 65nm 1P10M CMOS technology to verify the proposed scheme, which operates at the minimum energy point (0.3V) with 5.824pJ energy consumption for one write and one read operation.