Column-selection-enabled 8T SRAM array with ∼1R/1W multi-port operation for DVFS-enabled processors

Author

Park, Sang Phill ; Kim, Soo Youn ; Lee, Dongsoo ; Kim, Jae-Joon ; Griffin, W. Paul ; Roy, Kaushik

Author_Institution

Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA

fYear

2011

fDate

1-3 Aug. 2011

Firstpage

303

Lastpage

308

Abstract

In this work, we propose a new multi-port 8T SRAM architecture suitable for DVFS enabled processors. With multi-way caches using 8T SRAM, write-back operations are required to support column selection. While conventional write-back schemes may not have the 1R/1W dual port advantage of 8T SRAM, our proposed local write-back scheme preserves both ports with only minimal limitations. Simulation results show significant IPC enhancements with the proposed cache. Implementation in 45nm technology demonstrates wide-range DVFS (from 120MHZ@0.48V to 710MHz@1V) for the proposed SRAM array.

Keywords

SRAM chips; cache storage; microprocessor chips; power aware computing; two-port networks; DVFS-enabled processors; IPC enhancement; column selection enabled 8T SRAM array; instructions per cycle; multiport operation; multiway cache; one read-one write dual port; size 45 nm; write-back operation; Arrays; Cache memory; Decoding; Program processors; Random access memory; Transistors; 8T SRAM; Cache Memory; DVFS; Low-Power;

fLanguage

English

Publisher

ieee

Conference_Titel

Low Power Electronics and Design (ISLPED) 2011 International Symposium on

Conference_Location

Fukuoka

ISSN

Pending

Print_ISBN

978-1-61284-658-3

Electronic_ISBN

Pending

Type

conf

DOI

10.1109/ISLPED.2011.5993654

Filename

5993654