DocumentCode :
2888906
Title :
A biCMOS image signal processor with line memories
Author :
Kobayashi, Yoshiyuki ; Fukushima, Tetsuya ; Miura, Shun ; Kanasaki, M. ; Hirasawa, K. ; Asada, Kunihiro ; Jushi Ide ; Yamazaki, Kinya ; Tanihara, Y.
Author_Institution :
Hitachi Research Laboratory, Ibaraki-ken, Japan
Volume :
XXX
fYear :
1987
fDate :
0-0 Feb. 1987
Firstpage :
182
Lastpage :
183
Abstract :
An image signal processor which can operate on 512×512 TV images at a 25MHz pixel rate will be described. Two integrated line memories and time division of a parallel processor allow operation, such as 3×3 spatial convolutions, to be executed in realtime using 3 clock cycles. Device has been fabricated in a 1.8μm BiCMOS process with a die area of 104mm2.
Keywords :
BiCMOS integrated circuits; Convolution; Electronics packaging; Frequency; Image processing; Laboratories; Pixel; Process design; Signal processing; TV;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1987 IEEE International
Conference_Location :
New York, NY, USA
Type :
conf
DOI :
10.1109/ISSCC.1987.1157171
Filename :
1157171
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=2888906
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