• DocumentCode
    2888990
  • Title

    Layout methods to reduce CMOS stuck-open faults and enhance testability

  • Author

    Koeppe, S.

  • Author_Institution
    Siemens Research Laboratories, Munich, West Germany
  • Volume
    XXX
  • fYear
    1987
  • fDate
    0-0 Feb. 1987
  • Firstpage
    228
  • Lastpage
    229
  • Abstract
    CMOS layout rules that reduce the stuck-open faults by 30 to 40% and render the remaining detectagle with usual stuck-at test patterns, will be analyzed. The area penalty is less than 20%.
  • Keywords
    Automatic testing; CMOS logic circuits; Circuit faults; Circuit testing; Electrical fault detection; Fault detection; Laboratories; Logic testing; Semiconductor device modeling; Wiring;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference. Digest of Technical Papers. 1987 IEEE International
  • Conference_Location
    New York, NY, USA
  • Type

    conf

  • DOI
    10.1109/ISSCC.1987.1157176
  • Filename
    1157176
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2888990