PLATEST: A PLA test generator

Author

Raghuram, T.S. ; Hasan, M.M.

Author_Institution

Texas Instrum. Pvt. Ltd., Bangalore, India

fYear

1991

fDate

4-8 Jan 1991

Firstpage

288

Lastpage

289

Abstract

The growing use of PLAs in VLSI chips makes it imperative to have detailed study of the physical failures and the test generation. In this paper, physical failure analysis is carried out for NMOS PLA using SPICE simulation and the effects on the output of the PLA are studied. This study would be helpful in fault diagnosis and in improved design of the PLA. Based on these results the fault models are analysed and a novel test pattern generator, PLATEST, has been developed to generate minimal test set. PLATEST generates tests for all detectable cross-point faults and bridging faults. PLATEST has been implemented on a PC-AT in C(DOS)

Keywords

VLSI; circuit analysis computing; failure analysis; fault location; integrated circuit testing; logic arrays; logic testing; C(DOS); NMOS PLA; PC-AT; PLA test generator; PLATEST; SPICE simulation; VLSI chips; bridging faults; cross-point faults; fault diagnosis; fault models; minimal test set; physical failure analysis; programmable logic array; Analytical models; Failure analysis; Fault diagnosis; MOS devices; Pattern analysis; Programmable logic arrays; SPICE; Test pattern generators; Testing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, 1991. Proceedings., Fourth CSI/IEEE International Symposium on

Conference_Location

New Delhi

Print_ISBN

0-8186-2125-7

Type

conf

DOI

10.1109/ISVD.1991.185137

Filename

185137