A 98 GMACs/W 32-core vector processor in 65nm CMOS

Author

He, Xun ; Zhou, Dajiang ; Jin, Xin ; Goto, Satoshi

Author_Institution

Grad. Sch. of Inf., Production & Syst., Waseda Univ., Kitakyushu, Japan

fYear

2011

fDate

1-3 Aug. 2011

Firstpage

373

Lastpage

378

Abstract

This paper presents a high-performance dual-issue 32-core SIMD platform for image and video processing. Eight cores with a 4-ports L2 cache are connected by CIB bus as a cluster. Four clusters are connected by mesh network. The proposed hierarchical network can provide 192 GB/sintercore communication BW in average. To reduce coherence operation in large-scale SMP, an application specified protocol is proposed. Comparing with MOESI, 67.8% of L1 Cache energy can be saved in 32 cores case. It can achieve a peak performance of 375 GMACs and 98 GMACs/W in 65 nm CMOS.

Keywords

CMOS logic circuits; CMOS memory circuits; cache storage; microprocessor chips; network-on-chip; parallel processing; protocols; vector processor systems; video signal processing; 32-core vector processor; 4-ports L2 cache; CIB bus; CMOS circuits; L1 cache energy; NoC; application specified protocol; bit rate 192 Gbit/s; h igh-performance dual-issue 32-core SIMD platform; image processing; intercore communication BW; large-scale SMP; mesh network; network-on-chip; single instruction multiple data machines; size 65 nm; video processing; word length 32 bit; Coherence; Communication networks; Multicore processing; Multimedia communication; Pipelines; Protocols; Cache coherence; Multicore Processor; NoC; SIMD;

fLanguage

English

Publisher

ieee

Conference_Titel

Low Power Electronics and Design (ISLPED) 2011 International Symposium on

Conference_Location

Fukuoka

ISSN

Pending

Print_ISBN

978-1-61284-658-3

Electronic_ISBN

Pending

Type

conf

DOI

10.1109/ISLPED.2011.5993669

Filename

5993669