A fast, accurate and simple critical path monitor for improving energy-delay product in DVS systems

This paper introduces a design scheme that improves Energy-Delay Product (EDP) in conventional Dynamic Voltage Scaling (DVS) systems by exploiting timing margins. To achieve this scheme, we designed a high-speed Critical Path Monitor composed of several Critical Path Replicas, a Timing Checker, and a Toggle Flip-Flop. The replicas are implemented based on our proposed algorithm, which considers the following two facts: (a) the voltage scaling behavior of logic and interconnect are fundamentally different; (b) various logic gates show different sensitivity in regard to process, temperature, as well as voltage changes. Because the replicas are connected in parallel by C-elements, the longest delay selection among all of the replica delays is performed automatically, improving the system response time. If the utilizable margin is detected by the Timing Checker, the frequency controller increases system clock frequency in order to improve performance at a given voltage level. Using a 45nm CMOS technology, we implemented a 32-bit MIPS processor and multiple Critical Path Monitors. The simulation results reveal that our scheme can improve EDP of the conventional DVS by up to 62%.