DocumentCode
2889306
Title
A CMOS associative memory chip based on neural networks
Author
Graf, Hagen ; de Vegvar, P.
Author_Institution
AT&T Bell Laboratories, Holmdel, NJ, USA
Volume
XXX
fYear
1987
fDate
0-0 Feb. 1987
Firstpage
304
Lastpage
305
Abstract
This report will describe a chip containing 54 amplifiers, 6K SRAM and programmable interconnections, that has been used to implement an algorithm based on biological neural networks. The 75K transistor chip was fabricated in 25μm CMOS, measures 6.7×6.7mm and dissipates 500mW. Ten vectors stored in the memory may be recalled within 500ns.
Keywords
Associative memory; Biological neural networks; Brain modeling; Convergence; Coupling circuits; Integrated circuit interconnections; Neural network hardware; Neural networks; Operational amplifiers; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference. Digest of Technical Papers. 1987 IEEE International
Conference_Location
New York, NY, USA
Type
conf
DOI
10.1109/ISSCC.1987.1157193
Filename
1157193
Link To Document