A three dimensional register file for superscalar processors

The register file is a key datapath component of a superscalar microprocessor. Its access time is critical since it can impact cycle time. Its size can easily become a problem: superscalar microprocessors have a large number of ports (typically 10 for a three-scalar machine) and the size is quadratic in the number of ports. The “3D Register File ” uses the area inherently consumed by the metal wires used for the word and bit lines for each cell to hide N sets of registers. Each set is logically a plane in the third dimension. The ability to access multiple planes can be used for register windows or for extra register sets for real time tasks or microtask switching. The data array of a 3D eight-window 10 ported register file is six times smaller than a flat register file. Access time is sped up by shortening bus lines and by sharing a large buffer between bit cells. The 3D register file has been implemented on two high performance superscalar processors and early silicon confirms our simulations