Transient three-dimensional mixed-level circuit and device simulation: algorithms and applications

The authors describe algorithms for transient mixed-level circuit and device simulation using a two-carrier three-dimensional device simulator SIERRA and the circuit simulator SPICE3. It is pointed out that algorithms well suited to 2D mixed-level circuit and device simulation cannot be successfully used. The memory and CPU time requirements in 3D device simulation necessitate it the use of iterative solution techniques at the device level, which impose an additional constraint in developing efficient algorithms. Two node tearing schemes are shown to be the most promising schemes for coupling the circuit and device simulators. An application of 3D mixed-level simulation to the study of single-event upset of SRAM cells is presented.<>