Layout driven logic restructuring/decomposition

The authors present techniques to integrate interconnection optimization with logic restructuring and technology decomposition phases of logic synthesis. The approach is based on a point placement of a Boolean network which is used to guide the synthesis process by providing accurate estimates on wiring area and delay. The placement solution is incrementally updated as intermediate Boolean nodes are extracted or eliminated during the decomposition or elimination procedures. Combining these techniques with layout-driven technology mapping makes it possible to produce a synthesis solution and a ´companion´ placement solution for a given combinational logic circuit simultaneously. Using these techniques, circuits with smaller area and higher performance can be generated.<>