The nature of defect size distributions in semiconductor processes

Summary form only given. The combination of a small static random access memory (SRAM) and a test element group (TEG) has been shown to be an effective yield monitor for VLSI. Defects at all process levels are easily isolated, detected, and characterized through bit mapping and visual inspection. This not only provides an effective means for defect control at all process levels but also provides a unique opportunity to study the defect size distribution as a function of process and level. Defect size distributions have been measured for various process levels using a 1.25 μm CMOS SRAM/TEG yield monitor. These data have been analyzed with nonlinear regression techniques and show that the best fit model for the defect distribution is bi-modal and not a simple inverse power law as is usually presented in the literature. The nature of the bi-modal distribution is examined on a level by level basis as well as on a sub-level basis in terms of specific process operation. Evaluated in this manner, the resulting defect distribution is clearly shown to be highly dependent on the facility, process, and processing equipment