Title :
A 15MIPS 32b microprocessor
Author :
Yetter, J. ; Forsyth, M. ; Jaffe, W. ; Tanksalvala, D. ; Wheeler, J.
Author_Institution :
Hewlett-Packard, Fort Collins, CO, USA
Abstract :
A Reduced Instruction Set Computer using direct hardware instruction decode and 3-stage pipelined execution will be described. At an operating frequency of 30MHz, a 120Mbytes/s transfer rate on an external cache/coprocessor interface is achieved. NMOS technology is used to implement 115K transistors on an 8.4mm square chip.
Keywords :
Cache memory; Central Processing Unit; Circuits; Clocks; Decoding; Frequency; Microprocessors; Pipelines; Programmable logic arrays; Registers;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1987 IEEE International
Conference_Location :
New York, NY, USA
DOI :
10.1109/ISSCC.1987.1157220
