• DocumentCode
    2889891
  • Title

    Timing analysis and delay-fault test generation using path-recursive functions

  • Author

    McGeer, P.C. ; Saldanha, A. ; Stephan, P.R. ; Brayton, R.K. ; Sangiovanni-Vincentelli, A.L.

  • Author_Institution
    California Univ., Berkeley, CA, USA
  • fYear
    1991
  • fDate
    11-14 Nov. 1991
  • Firstpage
    180
  • Lastpage
    183
  • Abstract
    The authors introduce an efficient method for generating the functional forms of path analysis problems. They demonstrate that the resulting function is linear in the size of the circuit. The functions are then tested for satisfiability either using a Boolean network satisfiability algorithm suggested by T. Larrabee (1989) or through the construction of BDDs. The effectiveness of the proposed approach is shown for timing analysis and robust path delay-fault test generation. This method also holds promise for both static and dynamic hazard analysis, and for test generation using all other delay-fault models, tau -irredundant fault models, and stuck-open fault models.<>
  • Keywords
    delays; fault location; integrated circuit testing; logic testing; Boolean network satisfiability algorithm; delay-fault models; delay-fault test generation; dynamic hazard analysis; functional forms; path analysis; path-recursive functions; robust path delay-fault test generation; satisfiability; static hazard analysis; stuck-open fault models; tau -irredundant fault models; timing analysis; Algorithm design and analysis; Boolean functions; Circuit testing; Delay; Functional analysis; Hazards; Logic testing; Robustness; Timing; Wires;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer-Aided Design, 1991. ICCAD-91. Digest of Technical Papers., 1991 IEEE International Conference on
  • Conference_Location
    Santa Clara, CA, USA
  • Print_ISBN
    0-8186-2157-5
  • Type

    conf

  • DOI
    10.1109/ICCAD.1991.185225
  • Filename
    185225