The modular pipeline fast Fourier transform algorithm and architecture

This paper examines the modular pipeline fast Fourier transform algorithm and architecture. This algorithm couples a pair of √N-point FFT units with a center element to facilitate the efficient computation of N-point FFTs. The fundamental algorithm as well as an example pipeline FFT architecture are presented. Modular pipeline implementations substantially reduce the total number of delay elements. As a result, in a system where dynamic power is a concern, a reduction in total power consumption is achieved. The center element contains coefficient and data memory as well as addressing, routing, and control logic. This architecture encourages reusability in the FFT modules and provides equivalent throughput to conventional pipeline FFT architectures.