Embedded Jitter Measurement of High-speed I/O Signals

Author

Wang, Xueqing ; Eisenstadt, William R. ; Fox, Robert M.

Author_Institution

Dept. of Electr. & Comput. Eng., Florida Univ., Gainesville, FL

fYear

2007

fDate

27-30 May 2007

Firstpage

153

Lastpage

156

Abstract

In this paper, an embedded jitter measurement system is presented. The system uses the Vernier delay method to achieve high resolution. The jitter test circuit is implemented using current-mode logic, so it is fast enough for testing today´s high-speed I/O signals such as PCI Express. And the differential structure also makes the circuit immune to common-mode noise. Other advanced jitter measurement functions can be added to the time interval analyzer, (TIA) system presented here. Simulation results show that the TIA system can be used with low-cost ATEs to meet jitter measurement requirements

Keywords

automatic test equipment; current-mode logic; integrated circuit measurement; integrated circuit testing; jitter; logic testing; measurement systems; ATE; Vernier delay method; current-mode logic; differential structure; embedded jitter measurement system; high-speed I/O signals; jitter test circuit; time interval analyzer system; Circuit testing; Costs; Electric variables measurement; Gain measurement; Jitter; Logic testing; Oscillators; Signal resolution; System testing; Time measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on

Conference_Location

New Orleans, LA

Print_ISBN

1-4244-0920-9

Electronic_ISBN

1-4244-0921-7

Type

conf

DOI

10.1109/ISCAS.2007.378244

Filename

4252594