System design of a low-power I/O link

Author

Sridhara, S.R. ; Ganesh Balamurugan ; Shanbhag, Naresh R.

Author_Institution

ECE Dept, Illinois Univ., Urbana, IL, USA

Volume

2

fYear

2003

fDate

9-12 Nov. 2003

Firstpage

1468

Abstract

In this paper, we present a detailed analysis of the system design choices available for low-power high-speed I/O link transceivers. Using the transceiver power dissipation as the metric, we compare three equalization schemes (linear equalizer, decision-feedback equalizer, and transmit pre-emphasis) in combination with three pulse amplitude modulation (PAM) schemes (2-PAM, 4-PAM, and 8-PAM). The input signal levels and the filter lengths in the equalizer are chosen to minimize the power dissipation while meeting a bit error rate constraint. We show that, for a typical 20" intersymbol interference dominated link, transmit pre-emphasis in combination with 4-PAM results in 75 data rates.

Keywords

decision feedback equalisers; error statistics; intersymbol interference; pulse amplitude modulation; transceivers; PAM; bit error rate; decision-feedback equalizer; equalization scheme; filter length; high-speed I/O link transceiver; intersymbol interference; linear equalizer; low-power I/O link; power dissipation minimization; pulse amplitude modulation; system design; transceiver power dissipation; transmit pre-emphasis; Amplitude modulation; Bit error rate; Decision feedback equalizers; Filters; Interference constraints; Intersymbol interference; Power dissipation; Pulse modulation; System analysis and design; Transceivers;

fLanguage

English

Publisher

ieee

Conference_Titel

Signals, Systems and Computers, 2004. Conference Record of the Thirty-Seventh Asilomar Conference on

Print_ISBN

0-7803-8104-1

Type

conf

DOI

10.1109/ACSSC.2003.1292229

Filename

1292229