GALS Based Shared Test Architecture for Embedded Memories

Increasing memory content on SoCs, along with the shrinking technology node (resulting into newer kinds of defects), multiple clocks, and voltage domains necessitate a shared built in self test (BIST) capable of testing memories in different nooks of a chip with least routing congestion and the ability to handle different clock domains. Moreover, the BIST should be programmable so that it can cope up with upcoming defects. Hereby, we propose a shared and programmable BIST architecture based on GALS methodology to cater to the aforesaid needs