Title :
Built-in self-test in multi-port RAMs
Author :
Castro, A.V. ; Nicolaidis, M. ; Lestrat, P. ; Courtois, B.
Author_Institution :
IMAG/TIM3 Lab., Grenoble, France
Abstract :
The authors present a novel approach to the test of multi-port RAMs. A novel fault model that takes into account complex couplings resulting from simultaneous access of memory cells is used in order to ensure a very high fault coverage. A novel algorithm for the test of dual-port memories is detailed. This algorithm achieves O(n) complexity thanks to the use of some topological restrictions. The authors also present a novel built-in self-test (BIST) scheme, based on programmable schematic generators, that allows great flexibility for ASIC (application-specific integrated circuit) design.<>
Keywords :
VLSI; application specific integrated circuits; built-in self test; computational complexity; random-access storage; ASIC design flexibility; application-specific integrated circuit; built-in self-test; complexity; dual-port memories; fault coverage; multi-port RAM; programmable schematic generators; topological restrictions; Built-in self-test; Content addressable storage; Contracts; Decoding; Fault detection; Phased arrays; Random access memory; Read-write memory; Testing; Topology;
Conference_Titel :
Computer-Aided Design, 1991. ICCAD-91. Digest of Technical Papers., 1991 IEEE International Conference on
Conference_Location :
Santa Clara, CA, USA
Print_ISBN :
0-8186-2157-5
DOI :
10.1109/ICCAD.1991.185244
