Title :
Investigation of multi cell upset in sequential logic and validity of redundancy technique
Author :
Uemura, Taiki ; Kato, Takashi ; Matsuyama, Hideya ; Takahisa, Keiji ; Fukuda, Mitsuhiro ; Hatanaka, Kichiji
Author_Institution :
Fujitsu Semicond. Ltd., Tokyo, Japan
Abstract :
Purpose of this work is investigation of validity on redundancy techniques for soft-error mitigation in sequential elements such as flop-flops and latches. We have evaluated multi-cell-upset (MCU) in sequential elements through neutron acceleration experiments at Osaka Univ. We have calculated mitigation efficiency of the redundancy technique from the experimental results. MCU ratio increases with technology advancing. Validity of the redundancy technique is kept even on advanced technologies.
Keywords :
sequential circuits; MCU ratio; Osaka Univ; flop-flops; latches; mitigation efficiency; multicell upset; neutron acceleration experiments; redundancy technique; sequential elements; sequential logic; soft-error mitigation; Flip-flops; Latches; Layout; Logic gates; Neutrons; Redundancy; Tunneling magnetoresistance; MCU; charge sharing; flip-flop; latch; neutron; sequential element; soft error;
Conference_Titel :
On-Line Testing Symposium (IOLTS), 2011 IEEE 17th International
Conference_Location :
Athens
Print_ISBN :
978-1-4577-1053-7
DOI :
10.1109/IOLTS.2011.5993803
