DocumentCode :
2890478
Title :
Low voltage testing for interconnect opens under process variations
Author :
Moreno, Jesus ; Champac, Victor ; Renovell, Michel
Author_Institution :
Dept. of Electronic Engineering, National Institute for Astrophysics, Optics and Electronics-INAOE, Puebla, Mexico
fYear :
2012
fDate :
10-13 April 2012
Firstpage :
1
Lastpage :
6
Abstract :
Advances in test methodologies to deal with subtle behavior of some defects mechanisms as the technology scale are required. Among these interconnect opens are an important defect mechanism that requires detailed knowledge of its physical properties. Furthermore, in nanometer process variability is predominant and considering only nominal value of parameters is not realistic. In this work the detection capability of Low Voltage Testing for interconnect opens, considering process variations, is evaluated using a statistical model. To account for this the Probability of Detection of the defect is obtained. The proposed methodology is implemented in a software tool to determine the probability of detection of via opens for some ISCAS85 benchmark circuits. The results suggest that using Low Vdd in conjunction with favorable test vectors allow to improve the Probability of Detection of interconnect opens leading to better test quality.
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Workshop (LATW), 2012 13th Latin American
Conference_Location :
Quito, Ecuador
Print_ISBN :
978-1-4673-2355-0
Type :
conf
DOI :
10.1109/LATW.2012.6261231
Filename :
6261231
Link To Document :
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