Title :
Bipolar timing modeling including interconnects based on parametric correction
Author :
Yang, A.T. ; Chang, Y.-H.
Author_Institution :
Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
Abstract :
The authors present an approach for the analytical timing model development of bipolar VLSI circuits. The approach is based on the development of the delay functions of three basic bipolar subcircuits. It is shown that accurate timing information for two high-speed digital circuit constructs, ECL (emitter coupled logic) and BiCMOS, can be obtained by repeated processing of these subcircuit delay functions. The timing models have been shown to be accurate typically within 10% of SPICE´s estimates with up to three orders of speedup for large-scale BJT (bipolar junction transistor) circuits.<>
Keywords :
BIMOS integrated circuits; VLSI; bipolar integrated circuits; circuit analysis computing; emitter-coupled logic; BiCMOS; ECL; analytical timing model; bipolar VLSI circuits; delay functions; emitter coupled logic; high-speed digital circuit constructs; interconnects; parametric correction; Analytical models; BiCMOS integrated circuits; Coupling circuits; Delay; Digital circuits; Integrated circuit interconnections; Large-scale systems; Logic circuits; Timing; Very large scale integration;
Conference_Titel :
Computer-Aided Design, 1991. ICCAD-91. Digest of Technical Papers., 1991 IEEE International Conference on
Conference_Location :
Santa Clara, CA, USA
Print_ISBN :
0-8186-2157-5
DOI :
10.1109/ICCAD.1991.185274
