Bipolar timing modeling including interconnects based on parametric correction

The authors present an approach for the analytical timing model development of bipolar VLSI circuits. The approach is based on the development of the delay functions of three basic bipolar subcircuits. It is shown that accurate timing information for two high-speed digital circuit constructs, ECL (emitter coupled logic) and BiCMOS, can be obtained by repeated processing of these subcircuit delay functions. The timing models have been shown to be accurate typically within 10% of SPICE´s estimates with up to three orders of speedup for large-scale BJT (bipolar junction transistor) circuits.<>