A stimulus/response system based on hierarchical timing diagrams

The authors present a tool that captures timing specifications from hierarchical timing diagrams and models them using hierarchical constraint graphs. The main contribution of the present work is a novel algorithm that traverses the graph during simulation to generate stimuli and to validate circuit responses. The system, implemented in VHDL (VHSIC hardware description language), interacts with the circuit during simulation, thus allowing the generation of stimuli that depend on circuit responses. Experimental results are presented, and areas of future work are identified, such as the extension of the model to include inter-TD constraints, conditional execution semantics, and early firing events.<>