A multi-objective optimization for memory BIST sharing using a genetic algorithm

Author

Zaourar, Lilia ; Kieffer, Yann ; Wenzel, Arnaud

Author_Institution

SOC Dept., LIP6 Lab., Paris, France

fYear

2011

fDate

13-15 July 2011

Firstpage

73

Lastpage

78

Abstract

The memory BIST insertion involves the simultaneous optimization of several conflicting and competing objectives such as test time and power consumption during the test execution procedure. In this paper, a new memory BIST methodology is proposed which optimizes area overhead, test power and test time. It exploits Genetic Algorithms to find a set of Pareto optimal solutions. Since the designer is given a set of trade-off solutions between the three criteria, thus he can choose the most suitable one for his memory testing needs. The proposed algorithm is rigorously tested using several industrial designs.

Keywords

built-in self test; genetic algorithms; integrated circuit testing; memory architecture; genetic algorithm; memory BIST sharing; memory testing; multiobjective optimization; pareto optimal solutions; Biological cells; Built-in self-test; Genetic algorithms; Memory management; Optimization; Power demand; Multi-objective optimization; genetic algorithm; memory BIST;

fLanguage

English

Publisher

ieee

Conference_Titel

On-Line Testing Symposium (IOLTS), 2011 IEEE 17th International

Conference_Location

Athens

Print_ISBN

978-1-4577-1053-7

Type

conf

DOI

10.1109/IOLTS.2011.5993814

Filename

5993814