Converting combinational circuits into pipelined data paths

The authors present an algorithm which converts combinational circuits into pipelined data paths for a given clock period. The approach minimizes the number of registers, which is achieved by a recursive procedure selecting for each pipeline level those circuit parts where a register location satisfies the timing constraints. The selection is based on an as-soon-as-possible and as-late-as-possible register location using a modified retiming algorithm. Within these circuit parts a maximal flow algorithm guarantees that one finds the minimal number of flip-flops for a register. Because the algorithm runs in polynomial time and requires only a sparse graph representation of the circuit it is applicable to VLSI circuits. It is integrated into a synthesis tool for arithmetic building blocks, and results of its application to circuits of a size up to 10000 gates are presented.<>