DocumentCode
2890701
Title
Generic BIST architecture for testing of content addressable memories
Author
Grigoryan, H. ; Harutyunyan, G. ; Shoukourian, S. ; Vardanian, V. ; Zorian, Y.
fYear
2011
fDate
13-15 July 2011
Firstpage
86
Lastpage
91
Abstract
Minimal March test algorithms are developed for single-port binary and ternary content addressable memories (CAMs). Based on these test algorithms a built-in-self-test (BIST) architecture for testing of CAMs is proposed. It is an extension of an existing BIST architecture for testing of static random access memories (SRAMs) and read-only memories (ROMs). This generic BIST architecture additionally supports the following important CAM specific features: power buffer-zones, multicycle compare operations, half/quarter words and walking patterns.
Keywords
SRAM chips; built-in self test; content-addressable storage; read-only storage; CAM testing; ROM; SRAM; built-in-self-test architecture; content addressable memories testing; generic BIST architecture; read-only memories; static random access memories; Built-in self-test; Cams; Computer aided manufacturing; Computer architecture; Finite element methods; Microprocessors; BCAM; BIST architecture; CAM; March test algorithm; TCAM; fault;
fLanguage
English
Publisher
ieee
Conference_Titel
On-Line Testing Symposium (IOLTS), 2011 IEEE 17th International
Conference_Location
Athens
Print_ISBN
978-1-4577-1053-7
Type
conf
DOI
10.1109/IOLTS.2011.5993816
Filename
5993816
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