Efficient coherent detector VLSI design for continuous phase modulation

This paper presents a continuous phase modulation (CPM) coherent detector design suitable for high throughput, low power VLSI implementations. The key component of CPM coherent detector is the trellis decoder. Compared with the Viterbi algorithm, the sub-optimum T-algorithm significantly reduces computation complexity and provides great potential to realize low power trellis decoding. But it is not suitable for VLSI implementations because it contains search-the-best-metric operation as a throughput bottleneck and suffers from unstructured data manipulation. We propose an algorithm level technique to eliminate the throughput bottleneck in the original T-algorithm, leading to a new SPEC-T algorithm. A VLSI architecture for implementing the SPEC-T algorithm is developed, in which a token bus structure is used to solve the unstructured data manipulation problem.