Estimation of component criticality in early design steps

Nanoscale integrated circuits suffer both from high defect densities and increased parameter variations possibly affecting the overall timing behaviour. Components with a higher vulnerability to process variations are not just critical during test design and test application, but also during normal operation. In particular, ageing effects and changes in the operation environment including supply voltage, temperature and radiation, can easily aggravate the effects of parameter variations inherent to the manufacturing process. Online and offline techniques that attempt to cope with such effects, like online error detection and correction, online diagnosis and hardening, have high cost and therefore cannot be applied to the whole circuit. Making a good selection of components to apply these techniques to, requires accurate metrics for gate criticality under process variations. This paper presents a SAT-based approach to measure criticality. The algorithm requires a minimal amount of physical and electrical data, but it delivers a very good criticality estimate in a fraction of the time required by accurate statistical simulation. The results are validated by comparison to an exact simulation-based approach.