Title :
Ordering storage elements in a single scan chain
Author :
Gupta, R. ; Breuer, M.A.
Author_Institution :
IBM East Fishkill, Hopewell Junction, NY, USA
Abstract :
In serial scan designs, particularly those tested in a partitioned manner, the circuit test time is influenced by the ordering of the storage elements in the scan chain. A procedure for constructing a single serial scan chain with the objective of minimizing the overall test time is described. It uses a polynomial-time algorithm which results in an ordering of the storage elements along with an indication of the degree of optimality of the solution. The approach described is useful in minimizing the overall test time in full scan designs as well as in certain classes of partial scan designs.<>
Keywords :
integrated circuit testing; logic testing; degree of optimality; full scan designs; partial scan designs; polynomial-time algorithm; serial scan designs; single scan chain; storage elements ordering; Algorithm design and analysis; Circuit testing; Contracts; Costs; Design engineering; Kernel; Logic; Partitioning algorithms; Polynomials; Test pattern generators;
Conference_Titel :
Computer-Aided Design, 1991. ICCAD-91. Digest of Technical Papers., 1991 IEEE International Conference on
Conference_Location :
Santa Clara, CA, USA
Print_ISBN :
0-8186-2157-5
DOI :
10.1109/ICCAD.1991.185289
