A hierarchical methodology to improve channel routing by pin permutation

Author

Hou, C.Y. ; Chen, C.Y.R.

Author_Institution

Dept. of Electr. & Comput. Eng., Syracuse Univ., NY, USA

fYear

1991

fDate

11-14 Nov. 1991

Firstpage

440

Lastpage

443

Abstract

A hierarchical pin permutation algorithm is presented which is used as a preprocessor of conventional channel routing algorithms. This algorithm determines the proper positions of permutable gates and cell terminals such that the results of the subsequent channel routing can be significantly improved. First, gates and terminals are interchanged to maximize the number of aligned terminal pairs and to reduce the channel density. Then, terminals that are not aligned are interchanged to remove cyclic constraints in the vertical constraint graph (VCG). Experimental results show that the proposed algorithm considerably reduces the number of tracks and vias.<>

Keywords

circuit layout CAD; logic CAD; cell terminals; channel routing; cyclic constraints; gates; hierarchical methodology; permutable gates; pin permutation; preprocessor; terminals; vertical constraint graph; Algorithm design and analysis; Heuristic algorithms; Logic; Reflection; Routing; Terminology; Very large scale integration; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer-Aided Design, 1991. ICCAD-91. Digest of Technical Papers., 1991 IEEE International Conference on

Conference_Location

Santa Clara, CA, USA

Print_ISBN

0-8186-2157-5

Type

conf

DOI

10.1109/ICCAD.1991.185298

Filename

185298