Title :
A new test generation method for sequential circuits
Author :
Lee, D.H. ; Reddy, S.M.
Author_Institution :
Iowa Univ., Iowa City, IA, USA
Abstract :
A novel test generation method for synchronous sequential circuits is proposed. Among the new ideas employed are: (1) efficiently maintaining path information using an extended value system in forward time processing, and (2) efficiently enumerating cubes for state justification in backward time processing. Experimental results show that the proposed method is effective in generating high coverage tests for sequential circuits.<>
Keywords :
automatic testing; logic testing; sequential circuits; backward time processing; extended value system; forward time processing; path information; sequential circuits; state justification; test generation method; Circuit faults; Circuit testing; Cities and towns; Computer science; Flip-flops; Forward contracts; Logic arrays; Logic testing; Sequential analysis; Sequential circuits;
Conference_Titel :
Computer-Aided Design, 1991. ICCAD-91. Digest of Technical Papers., 1991 IEEE International Conference on
Conference_Location :
Santa Clara, CA, USA
Print_ISBN :
0-8186-2157-5
DOI :
10.1109/ICCAD.1991.185300
