DocumentCode
2890983
Title
Test generation for synchronous sequential circuits based on fault extraction
Author
Pomeranz, I. ; Reddy, S.M.
Author_Institution
Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
fYear
1991
fDate
11-14 Nov. 1991
Firstpage
450
Lastpage
453
Abstract
The authors describe an efficient procedure for translating stuck-at faults in a gate level implementation into state-table faults in a state-table description of the circuit. Based on this fault procedure, a test generation approach is presented for stuck-at faults, which results in short test sequences and achieves complete coverage of stuck-at faults. Experimental results are given for both MCNC and ISCAS-89 benchmark circuits, to demonstrate the applicability of the method.<>
Keywords
automatic testing; fault location; logic testing; sequential circuits; ISCAS-89 benchmark circuits; MCNC; fault extraction; gate level implementation; state-table description; state-table faults; stuck-at faults; synchronous sequential circuits; test generation; test generation approach; Benchmark testing; Circuit faults; Circuit testing; Cities and towns; Computational efficiency; Fault detection; Polynomials; Sequential analysis; Sequential circuits; Synchronous generators;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer-Aided Design, 1991. ICCAD-91. Digest of Technical Papers., 1991 IEEE International Conference on
Conference_Location
Santa Clara, CA, USA
Print_ISBN
0-8186-2157-5
Type
conf
DOI
10.1109/ICCAD.1991.185301
Filename
185301
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