A signal-driven discrete relaxation technique for architectural level test generation

A novel architectural level test generation methodology is proposed to solve both data flow path conflicts and data flow value conflicts. For each pattern to be justified at a high level, an instruction sequence and the underdetermined system of nonlinear equations are derived based on preprocessing information. The solution of the system of equations is calculated by a signal-driven discrete relaxation algorithm without making any high-level decisions. The test generation is performed by recursively assembling the instruction sequence and solving the system of equations. This test generation approach has been implemented, and the tests of several microprocessors have been generated successfully. The results show that this approach is effective and promising.<>