A convex optimization approach to transistor sizing for CMOS circuits

The transistor sizing problem of minimizing the circuit area, subject to the circuit delay being less than a given specification, is formulated as a convex programming problem. An efficient convex programming algorithm is then used to obtain the exact solution. Experimental results on a variety of circuits show that, for a given delay specification this approach is able to produce circuits with significantly smaller area when compared with TILOS.<>