A verification strategy for fault-detection and fault-tolerance circuits

Dependability, availability, reliability and security (in a single word, robustness) are primary-importance elements for today´s Systems-on-Chip (SoCs), in different areas. To achieve robustness, functional blocks are combined with fault-detection and fault-tolerance circuits to detect or correct faults due to environmental impact, aging, soft-errors and so forth. Furthermore, systematic faults (i.e. fault whose failure is manifested in a deterministic way) shall be avoided. Fault-detection and fault-tolerance circuits´ verification is the key to achieve that goal. This paper summarizes the state-of-the-art for verification-by-simulation flow, to subsequently extend the verification strategy for fault-detection and fault-tolerance circuits.