Two-dimensional layout synthesis for large-scale CMOS circuits

The authors propose an algorithm for automatically generating a mask pattern from the logical description of a large-scale CMOS circuit, i.e., ´macro´, consisting of up to several thousands of transistors. The layout model considered is a 2-D or ´multi-row´ model which is composed of a set of rows of paired PMOS and NMOS transistors. The large-scale layout synthesis is attained by combining an effective 1-D layout synthesis and a standard cell layout algorithm in divide-and-conquer style. For a practical circuit, the proposed algorithm yields an 18% smaller layout than the conventional standard cell approach.<>