Title :
A systematic approach for designing testable VLSI circuits
Author :
Lin, S.-P. ; Njinda, C.A. ; Breuer, M.A.
Author_Institution :
Dept. of Electr. Eng.-Syst., Univ. of Southern California, Los Angeles, CA, USA
Abstract :
A systematic approach has been developed to provide designers with a set of testable versions for a given design, ranging from the minimal test time solution to the minimal area overhead solution. The designer thus has the flexibility to make the necessary tradeoff between area overhead and test time depending on the constraints of the design under consideration. By employing an expert selection developed previously, the system can be extended to operate as an intelligent BIST (built-in self-test) design advisor. Experiments have been performed on several circuits generated by MABAL, a high-level synthesis tool, to demonstrate the performance of this approach.<>
Keywords :
VLSI; built-in self test; circuit CAD; integrated circuit testing; BIST; MABAL; built-in self-test; high-level synthesis tool; minimal area overhead solution; minimal test time solution; systematic approach; testable VLSI circuit design; testable versions; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Integer linear programming; Kernel; Registers; Resource management; System testing; Very large scale integration;
Conference_Titel :
Computer-Aided Design, 1991. ICCAD-91. Digest of Technical Papers., 1991 IEEE International Conference on
Conference_Location :
Santa Clara, CA, USA
Print_ISBN :
0-8186-2157-5
DOI :
10.1109/ICCAD.1991.185314
