DocumentCode :
2891175
Title :
Efficient code generation for digital signal processors with parallel and pipelined instructions
Author :
Hwang, Yin-Tsung ; Hwang, Jer-Sho
Author_Institution :
Dept. of Electron. Eng., Nat. Yunlin Inst. of Technol., Taiwan
fYear :
1997
fDate :
3-5 Nov 1997
Firstpage :
243
Lastpage :
252
Abstract :
Modern digital signal processors are capable of performing multiple pipelined instructions concurrently. However, strict and complicated coding rules, mostly due to the limitation of the processor´s internal structures, must be observed to achieve the full performance. These include the proper selection of operand data types, efficient usage of data and address registers, and novel instruction scheduling to support parallel execution without pipeline conflicts. In this paper, a progressive code generation scheme based on a simulated evolution algorithm is devised. In this scheme, the selection of operand data type is embedded in instruction scheduling so that appropriate choices can be made to support parallel instruction. Instruction scheduling and register allocation, however, are performed in an interleaving and iterative manner. In each iteration, the generated code quality is evaluated and the inferior part is rescheduled. Tested benchmark programs indicate that our scheme can outperform the TI DSP processor C compiler and generate very efficient assembly codes
Keywords :
automatic programming; digital signal processing chips; genetic algorithms; instruction sets; parallel programming; pipeline processing; program compilers; resource allocation; scheduling; software performance evaluation; software quality; C compiler; TI DSP processor; address registers; assembly codes; benchmark programs; code generation; code quality; coding rules; data registers; digital signal processors; instruction scheduling; multiple concurrent instructions; operand data types; parallel instructions; performance; pipelined instructions; register allocation; simulated evolution algorithm; Benchmark testing; Digital signal processing; Digital signal processors; Interleaved codes; Iterative algorithms; Pipelines; Processor scheduling; Registers; Signal generators; Signal processing algorithms;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Signal Processing Systems, 1997. SIPS 97 - Design and Implementation., 1997 IEEE Workshop on
Conference_Location :
Leicester
ISSN :
1520-6130
Print_ISBN :
0-7803-3806-5
Type :
conf
DOI :
10.1109/SIPS.1997.626131
Filename :
626131
Link To Document :
بازگشت