Title :
Design for easily applying test vectors to improve delay fault coverage
Author :
Sha, E.H.-M. ; Chao, L.-F.
Author_Institution :
Dept. of Comput. Sci., Princeton Univ., NJ, USA
Abstract :
It has been noted that arbitrary test pairs ( nu /sub 1/, nu /sub 2/) cannot be applied to a combinational pair of a finite state machine using standard scan path design. The scan path design is a special case of test machines which are designed to control and observe the object machine for detecting faults. By studying state transition graphs, the authors propose a general framework, which is composed of two stages, to solve this problem. Given a set of test pairs and a set of test machines, the first stage is to select a test machine which has the maximum delay fault coverage. If the fault coverage is not satisfactory, two approaches are proposed at the second stage. It is shown that these two optimization problems in the second stage are both NP-hard. Three algorithms are designed to solve these problems.<>
Keywords :
computational complexity; delays; finite automata; logic testing; optimisation; NP-hard; arbitrary test pairs; delay fault coverage; easily applying test vectors; finite state machine; maximum delay fault coverage; optimization problems; state transition graphs; Algorithm design and analysis; Automatic testing; Chaos; Circuit faults; Circuit testing; Computer science; Delay; Fault detection; Latches; Test pattern generators;
Conference_Titel :
Computer-Aided Design, 1991. ICCAD-91. Digest of Technical Papers., 1991 IEEE International Conference on
Conference_Location :
Santa Clara, CA, USA
Print_ISBN :
0-8186-2157-5
DOI :
10.1109/ICCAD.1991.185315