The impedance fault model and design for robust impedance fault testability

It is pointed out that advanced submicron CMOS processes result in failure mechanisms that tend to be increasingly analog in nature. They are not adequately covered by stuck-at, stuck-on, or stuck-open models. Furthermore, delay faults, spot defect models, and IDDQ approaches only cover restricted subsets of the dominant failure mechanisms. The impedance fault model forms a superset of all the above fault models while explicitly addressing the analog nature of the failures. An associated design methodology for robust impedance fault testability (DRIFT) provides robustly testable general structures with less area overhead than other transistor level DFT techniques and negligible speed penalties. DRIFT is especially well-suited for gate array, standard cell, and synthesized designs. The effects of process and device level variabilities of the IC are directly represented as variations of the channel impedance characteristics. The DRIFT techniques then transform the channel impedance difference into logic level changes at the CMOS structure output.<>