Title :
Fault simulation for multiple faults using shared BDD representation of fault sets
Author :
Takahashi, N. ; Ishiura, N. ; Yajima, S.
Author_Institution :
Dept. of Inf. Sci., Kyoto Univ., Japan
Abstract :
The authors propose a novel fault simulation technique for multiple faults. In order to handle a large number of multiple faults, sets of multiple faults are represented by Boolean functions, in which shared binary decision diagrams (BDDs) are used as an internal representation of Boolean functions. The authors also propose a fault dropping method, prime fault dropping, which is used efficiently to execute multiple fault simulation. The authors have succeeded in simulating 39 million double faults of a circuit of 2300 gates with about 20 Mbyte storage.<>
Keywords :
Boolean functions; circuit analysis computing; fault location; logic CAD; logic testing; Boolean functions; fault dropping method; fault sets; fault simulation; multiple faults; prime fault dropping; shared BDD representation; shared binary decision diagrams; Binary decision diagrams; Boolean functions; Circuit faults; Circuit simulation; Circuit testing; Computational efficiency; Computational modeling; Fault diagnosis; Information systems; Systems engineering and theory;
Conference_Titel :
Computer-Aided Design, 1991. ICCAD-91. Digest of Technical Papers., 1991 IEEE International Conference on
Conference_Location :
Santa Clara, CA, USA
Print_ISBN :
0-8186-2157-5
DOI :
10.1109/ICCAD.1991.185329