An efficient 2-D DWT processor architecture based on state space implementation technique

This work presents an efficient processor architecture which is constructed by filter bank or lifting scheme for real time processing of separable 2-D discrete wavelet transform (DWT). To achieve high efficiency, we use the partitioning algorithm based on the state space representation technique and RPA-like scheme. As a result, the architecture can reduce the critical path by the state space implementation. It has smaller hardware resources compared to that of other architectures with comparable throughput by the improvement of hardware utilization.